Digital Backend Engineer

Who we are

Move Silicon is the business unit of Move S.p.A. dedicated to the development of high-efficiency ASIC and SoC solutions for industrial, automotive, and IoT applications.
We work in close collaboration with global customers to bring innovative analog and mixed-signal devices to market, with a strong focus on the reliability and sustainability of our projects.

The role

We are building a new team of highly qualified engineers to tackle the most complex challenges in digital backend design, with a focus on innovation and technical excellence.
For this purpose, we are looking for a Digital Backend Engineer with solid experience in the physical design (RTL-to-GDS) of complex ASICs and SoCs.
The role will be responsible for floorplanning, place-and-route, timing closure, and sign-off verification, ensuring that our devices meet performance, area, and power targets before tape-out.

Key responsibilities

• Synthesis and floorplanning starting from RTL netlists, defining macro placement, routing channels, and power grids.
• Place-and-route using Cadence Innovus, Synopsys ICC2/Fusion Compiler, or Siemens Aprisa, with a focus on congestion, timing, and DRC.
• Clock Tree Synthesis (CTS) and optimization of skew, jitter, and insertion delay.
• Static Timing Analysis (STA) using PrimeTime or Tempus, including setup/hold closure and multi-corner critical path analysis.
• Power and IR-drop analysis and integration of low-power techniques such as UPF, DVFS, and power gating.
• Physical verification including DRC/LVS, EM/IR analysis, and layout sign-off using Calibre or Pegasus.
• Automation scripting in TCL, Python, and Bash for P&R flows and verification regressions on server farms.
• Generation of technical documentation and status reports for digital designers, layout teams, and management.
• Mentorship of junior engineers and interface with foundries and external package and test service providers.

Requirements

Must-have

4–5 years of experience in ASIC or SoC backend/physical design.

A Master’s degree in Electronic Engineering, Computer Engineering, or an equivalent field.

Strong proficiency with Innovus, ICC2, or Aprisa, as well as PrimeTime or Tempus.

Solid skills in CTS, STA, DRC/LVS, and multi-corner timing closure.

Ability to write automation scripts in TCL and Python and to use Git-based version control systems.

Nice-to-have

Experience with FinFET technology nodes at 7 nm or below.

Advanced low-power implementations including UPF and active clock gating.

EM/IR sign-off experience using tools such as Voltus or RedHawk.

Integration of high-speed IPs such as PCIe, DDR, and SerDes.

Knowledge of automotive standards and requirements including ISO 26262 and AEC-Q100.

What we offer

• Economics: permanent contract under the Commerce CCNL with electronic meal vouchers.
• Growth: a dynamic environment that promotes innovation and continuous training, including EDA tool courses and conferences such as DATE and ISPD.
• Location: offices in the heart of Milan, close to public transport and services.
• Social life: regular team-building activities and events to strengthen team spirit.
• Benefits: annual performance-based bonus, internal cafeteria or meal vouchers, and health insurance.

Work locations

Via Marcantonio Colonna 35, 20149 Milan – smart working available.
Via Carlo Piaggia 421, 55100 Lucca – smart working available.

How to apply

Send an updated CV to careers@move-x.it with the subject line “Digital Backend Engineer – Physical Design & Sign-off”.
Only candidates meeting the must-have requirements will be considered.
Move Silicon promotes equal opportunities and welcomes applications regardless of gender, orientation, ethnicity, or personal beliefs.
Candidates of all genders are welcome (pursuant to Law 903/77). Please read our privacy notice pursuant to Art. 13 of Regulation (EU) 2016/679 (GDPR).

Chi siamo

Move-X è la business unit di Move S.p.A. dedicata allo sviluppo di soluzioni ASIC e SoC ad alta efficienza per applicazioni industriali, automotive e IoT. Lavoriamo in stretta collaborazione con clienti globali per portare sul mercato dispositivi analogici e mixed-signal innovativi, con un forte focus sull’affidabilità e sulla sostenibilità dei nostri progetti.

La posizione

Stiamo costruendo un nuovo team di ingegneri altamente qualificati per affrontare le sfide più complesse sul digital backend, con un focus sull’innovazione e sull’eccellenza tecnica.

Cerchiamo a tale scopo un/una Digital Backend Engineer con solida esperienza nella progettazione fisica (RTL-to-GDS) di ASIC/SoC complessi. La figura sarà responsabile di floor-planning, place-&-route, timing closure e verifiche di sign-off, assicurando che i nostri dispositivi rispettino gli obiettivi di prestazioni, area e potenza prima del tape-out.

Responsabilità principali

• Synthesis e floor-planning a partire da netlist RTL, definendo macro placement, channel e power grid.
• Place-&-Route (Cadence Innovus, Synopsys ICC2/ Fusion Compiler, Siemens Aprisa) con focus su congestione, timing e DRC.
• Clock-Tree Synthesis (CTS) e ottimizzazione di skew, jitter e insertion delay.
• Static Timing Analysis (STA) con PrimeTime o Tempus, chiusura di hold/set-up e path criticali multi-corner.
• Power e IR-drop analysis, integrazione di tecniche low-power (UPF, DVFS, power gating).
• Physical verification (DRC/LVS), EM/IR e sign-off di layout con Calibre o Pegasus.
• Script di automazione (TCL, Python, Bash) per flussi P&R e regressioni di verifica su server farm.
• Generazione di documentazione tecnica e report di stato per designer digitali, layout e management.
• Mentorship di profili junior e interfaccia con foundry e service house di package & test.

Requisiti

Must-have

4-5 anni di esperienza in backend/physical design ASIC o SoC

Laurea magistrale in Ingegneria Elettronica/Informatica (o equivalente)

Padronanza di Innovus/ICC2/Aprisa e PrimeTime/Tempus

Competenze di CTS, STA, DRC/LVS e chiusura timing multi-corner

Capacità di scripting in TCL/Python e uso di Git

Nice-to-have

Esperienza su nodi FinFET ≤ 7 nm

Implementazioni low-power avanzate (UPF, active clock gating)

Sign-off EMIR (Voltus, RedHawk)

Integrazione IP ad alta velocità (PCIe, DDR, SerDes)

Conoscenza requisiti ISO 26262/AEC-Q100 per automotive

Cosa offriamo

• Economics: tempo indeterminato CCNL Commercio + buoni pasto elettronici.
• Crescita: ambiente dinamico che favorisce innovazione e formazione continua (corsi tool EDA, conferenze DATE/ISPD).
• Sede: uffici nel cuore di Milano, vicino a trasporti pubblici e servizi.
• Socialità: team-building ed eventi regolari per rafforzare lo spirito di squadra.
• Benefit: bonus annuale legato ai risultati, mensa interna/buoni pasto, assicurazione sanitaria.

Sede di lavoro

Via Marcantonio Colonna 35, 20149 Milano – possibilità di smart working.

Via Carlo Piaggia 421, 55100 Lucca – possibilità di smart working.

Come candidarsi

 Invia CV aggiornato a careers@move-x.it indicando nell’oggetto “Digital Backend Engineer – Physical Design & Sign-off”. Saranno presi in considerazione solo i profili che soddisfano i requisiti must-have.

Move-X promuove le pari opportunità: accogliamo candidature senza distinzione di genere, orientamento, etnia o convinzioni personali.

 Accogliamo candidati di ogni genere (ai sensi della Legge 903/77). Ti invitiamo a leggere la nostra informativa sulla privacy, art. 13 del regolamento (UE) 2016/679 sulla protezione dei dati (GDPR).